Module Specification |
The information contained in this module specification was correct at the time of publication but may be subject to change, either during the session because of unforeseen circumstances, or following review of the module at the end of the session. Queries about the module should be directed to the member of staff with responsibility for the module. |
Title | Embedded Computer Systems | ||
Code | ELEC370 | ||
Coordinator |
Dr S Khursheed Electrical Engineering and Electronics S.Khursheed@liverpool.ac.uk |
||
Year | CATS Level | Semester | CATS Value |
Session 2022-23 | Level 6 FHEQ | First Semester | 15 |
Aims |
|
To obtain an understanding of the construction and operation of embedded computer systems and their components. Furthermore to gain an understanding of how computer performance is dependent upon the design of computer architectures and sub-circuits. |
Pre-requisites before taking this module (other modules and/or general educational/academic requirements): |
ELEC211 Digital Electronics & Microprocessor Systems |
Co-requisite modules: |
Learning Outcomes |
|
(LO1) An understanding of the internal operation of a CPU |
|
(LO2) Knowledge of some methods used to increase CPU performance |
|
(S1) On successful completion of the module, students should be able to show experience and enhancement of the following key skills: Independent learning Problem solving and design skills. |
|
(S2) After successful completion of the module: students should be able to determine how any computer system functions from published data and be able to apply this to developing simple processor systems from large scale modules. |
|
(S3) On successful completion of the module: the student should be able to understand published data concerning use of typical computer system components. |
|
(S4) After successful completion of the module, the student should have: An understanding of the internal operation of a CPU Knowledge of some methods used to increase CPU performance, an understanding of the difference between RISC and CISC type systems and knowledge of memory systems. |
Syllabus |
|
- Characteristics of Embedded Systems. Low power, design reuse, open standards, IP 2 Computer Architecture von Neumann structure, standard CPU architecture, characteristics and comparison of CISC and RISC systems - ALU architecture requirements of the ALU, number representation and ALU sub-circuits. - Memory cache performance measures, direct mapped, associative cache design, write strategies. - Thumb instruction set characteristics, performance benefits. - Low power digital circuit design voltage scaling, clock gating, power gating. - Bus architectures tri-state bus, AMBA, bus decoders, bus arbiters, APB, AHB, etc. - Memory management MPU, MMU, virtual addresses, page tables, PTW and translation look-aside buffer extension to multiple OS systems. |
Teaching and Learning Strategies |
|
Due to Covid-19, one or more of the following delivery methods will be implemented based on the current local conditions and the situation of registered students. It is anticipated that both a) & b) will be in operation for semester 1. Teaching Method 2 - Synchronous face to face tutorials (b) Fully online delivery and assessment Teaching Method 2 - On-line synchronous tutorials (c) Standard on-campus delivery with minimal social distancing Teaching Method 2 - Tutorial |
Teaching Schedule |
Lectures | Seminars | Tutorials | Lab Practicals | Fieldwork Placement | Other | TOTAL | |
Study Hours |
48 |
6 |
54 | ||||
Timetable (if known) | |||||||
Private Study | 96 | ||||||
TOTAL HOURS | 150 |
Assessment |
||||||
EXAM | Duration | Timing (Semester) |
% of final mark |
Resit/resubmission opportunity |
Penalty for late submission |
Notes |
(370) Final Exam Assessment 1 Assessment Schedule (When) :Semester 1 examination period | 0 | 75 | ||||
(370.1) Class Test | 1 | 25 | ||||
CONTINUOUS | Duration | Timing (Semester) |
% of final mark |
Resit/resubmission opportunity |
Penalty for late submission |
Notes |
Reading List |
|
Reading lists are managed at readinglists.liverpool.ac.uk. Click here to access the reading lists for this module. |