Module Specification |
The information contained in this module specification was correct at the time of publication but may be subject to change, either during the session because of unforeseen circumstances, or following review of the module at the end of the session. Queries about the module should be directed to the member of staff with responsibility for the module. |
Title | Digital System Design | ||
Code | ELEC473 | ||
Coordinator |
Professor JS Smith Electrical Engineering and Electronics J.S.Smith@liverpool.ac.uk |
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Year | CATS Level | Semester | CATS Value |
Session 2022-23 | Level 7 FHEQ | Whole Session | 15 |
Aims |
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To provide students with the ability to: Design and synthesise digital systems using Verilog and ASM. Understand the problems of meta-stability in digital systems. Design microprocessors using ASM techniques. Develop and test customised NIOS II systems using Altera's System on a Programmable Chip (SOPC) builder tool and Software Build Tools (SBT). |
Pre-requisites before taking this module (other modules and/or general educational/academic requirements): |
ELEC211 Digital Electronics & Microprocessor Systems |
Co-requisite modules: |
Learning Outcomes |
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(LO1) Ability to design digital systems using the ASM design method. |
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(LO2) Ability to implement digital systems using the Verilog Hardware Description Language. |
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(LO3) Understanding the internal operation of a MIPS processor. |
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(LO4) Ability to implement a SOPC system using Quartus Nios-II. |
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(S1) IT skills. |
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(S2) Problem solving skills. |
Syllabus |
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1. Introducing Verilog for logic design and the required software and hardware tools for the assignments. |
Teaching and Learning Strategies |
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Due to Covid-19, one or more of the following delivery methods will be implemented based on the current local conditions. Teaching Method 2 - On-line synchronous tutorials Teaching Method 3 - Campus based Laboratory Work Tutorials (b) Fully online delivery and assessment Teaching Method 2 - On-line synchronous tutorials Teaching Method 3 - on-line Laboratory Work Tutorials (c) Standard on-campus delivery with minimal social distancing Teaching
Method 2 - Tutorial Teaching Method 3 - Laboratory Work |
Teaching Schedule |
Lectures | Seminars | Tutorials | Lab Practicals | Fieldwork Placement | Other | TOTAL | |
Study Hours |
24 |
4 |
60 |
88 | |||
Timetable (if known) | |||||||
Private Study | 62 | ||||||
TOTAL HOURS | 150 |
Assessment |
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EXAM | Duration | Timing (Semester) |
% of final mark |
Resit/resubmission opportunity |
Penalty for late submission |
Notes |
(473.4) Open Book Class Test 1 There is a resit opportunity. This is not an anonymous assessment. Assessment Schedule (When) :Week 12 Semester 1 | 0 | 10 | ||||
(473.5) Open Book Class Test 2 There is a resit opportunity. This is not an anonymous assessment. Assessment Schedule (When) :Week 12 Semester 2 | 0 | 10 | ||||
CONTINUOUS | Duration | Timing (Semester) |
% of final mark |
Resit/resubmission opportunity |
Penalty for late submission |
Notes |
(473.3) Basic Verilog design example There is a resit opportunity. Standard UoL penalty applies for late submission. This is not an anonymous assessment. Assessment Schedule (When) :Submit Wee | 0 | 15 | ||||
(473.1) Verilog design example There is a resit opportunity. Standard UoL penalty applies for late submission. This is not an anonymous assessment. Assessment Schedule (When) :Week 12 Semester | 0 | 25 | ||||
(473.2) MIPS Processor Design and Implementation There is a resit opportunity. Standard UoL penalty applies for late submission. This is not an anonymous assessment. Assessment Schedule (When) | 0 | 20 | ||||
(473) NIOS II - Design example There is a resit opportunity. Standard UoL penalty applies for late submission. This is not an anonymous assessment. Assessment Schedule (When) :Submit Week 12 - | 0 | 20 |
Reading List |
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Reading lists are managed at readinglists.liverpool.ac.uk. Click here to access the reading lists for this module. |