Module Specification
The information contained in this module specification was correct at the time of publication but may be subject to change, either during the session because of unforeseen circumstances, or following review of the module at the end of the session. Queries about the module should be directed to the member of staff with responsibility for the module.
Title CMOS Integrated Circuits
Code ELEC212
Coordinator Dr I Mitrovic
Electrical Engineering and Electronics
Ivona@liverpool.ac.uk
Year CATS Level Semester CATS Value
Session 2022-23 Level 5 FHEQ Second Semester 7.5

Aims

To combine CMOS integrated circuits design activity with very relevant industrial concepts and a deeper understanding of MOSFET device physical principles and electromagnetism. To provide the background for later modules, relevant final year projects, but particularly for employment in those industries that are firmly based in microelectronics technology.


Pre-requisites before taking this module (other modules and/or general educational/academic requirements):
 

Co-requisite modules:
 

Learning Outcomes

(LO1) Properties of silicon (derivation of energy band diagram from quantum-mechanical principles, conductivity and mobility) and doping to engineer semiconductor p- or n-type

(LO2) Fundamentals on PN junction and MOS capacitor physics

(LO3) Fundamentals on MOSFET and CMOS devices (detailed understanding of device operation, regimes of operation, transfer characteristics)  

(LO4) Fundamentals on CMOS fabrication technology: processing, layout and design issues

(LO5) Basic CMOS logic families

(LO6) Advanced digital CMOS circuits: pseudo n-MOS and dynamic logic principles and design issues

(LO7) Domino logic gates: principles, advantages and disadvantages

(S1) On successful completion of the module, students should be able to show experience and enhancement of the following key transferable skills: Independent learning; Problem solving; Design skills; Drawing skills and Report writing skills.

(S2) After successful completion of the module, the student should have the following practical skills: the ability to analyse and design simple CMOS logic gates and amplifier stages.

(S3) On successful completion of the module, students should be able to demonstrate intellectual ability in applying knowledge of the above topics to determine the design consideration when working with MOS integrated circuits.

(S4) After successful completion of the module, the student should have knowledge and understanding in
i) Appreciation of MOS based integrated circuit design philosophy: power, speed, yield, packing density

ii) Considerations and of design trade-offs associated with materials, device and circuit limitations.

iii) Appreciation of historical and future development of silicon-based integrated circuit technology.

Syllabus
 

Properties of silicon: Wave mechanics, E.k diagram, energy gap, conductivity and mobility.

Simple two terminal devices: MOS capacitor and pn junction. Built-in potential and capacitance.

MOS Logic families: Basic operation, transfer characteristics, inverter compatibility through load lines.

CMOS fabrication processing, layout and design issues (includes design assignment exercise): demanding; detailed understanding of device operation appreciation of layout principles and area minimisation development of drawing skills development of report presentation skills

CMOS circuits: NAND, NOR, realisation of more complex combinational gates, speed and power dissipation

Advanced Digital CMOS circuits: Pseudo N-MOS and dynamic logic principles

Domino Logic: Principles, advantages and disadvantages.

Revision.

Introduction of advanced problems.

Teaching and Learning Strategies

Due to Covid-19, one or more of the following delivery methods will be implemented based on the current local conditions and the situation of registered students.
(a) Hybrid delivery, with social distancing on Campus
Teaching Method 1 - On-line asynchronous lectures
Description: Lectures to explain the material
Attendance Recorded: No
Notes: On average one per week

Teaching Method 2 - Synchronous face to face tutorials
Description: Tutorials on the Assignments and Problem Sheets
Attendance Recorded: Yes
Notes: On average one per fortnight

(b) Fully online delivery and assessment
Teaching Method 1 - On-line asynchronous lectures
Description: Lectures to explain the material
Attendance Recorded: No
Notes: On average one per week

Teaching Method 2 - On-line synchronous tutorials
Description: Tutorials on the Assignments and Problem Sheets
A ttendance Recorded: Yes
Notes: On average one per fortnight

(c) Standard on-campus delivery with minimal social distancing
Teaching Method 1 - Lecture
Description: Lectures to explain the material
Attendance Recorded: Yes
Notes: On average one per week

Teaching Method 2 - Tutorial
Description: Tutorials on the Assignments and Problem Sheets
Attendance Recorded: Yes
Notes: On average one per fortnight

Teaching Schedule
  Lectures Seminars Tutorials Lab Practicals Fieldwork Placement Other TOTAL
Study Hours 12

   6

     2

 20
Timetable (if known)              
Private Study 55
TOTAL HOURS 75

Assessment
EXAM Duration Timing
(Semester)		 % of
final
mark		 Resit/resubmission
opportunity		 Penalty for late
submission		 Notes
(212) Assessment 2 There is a resit opportunity. Standard UoL penalty applies for late submission. Assessment Schedule (When) :Semester 2 examination period  0    75       
CONTINUOUS Duration Timing
(Semester)		 % of
final
mark		 Resit/resubmission
opportunity		 Penalty for late
submission		 Notes
(212.1) Assessment 1 There is a resit opportunity. Standard UoL penalty applies for late submission. Assessment Schedule (When) :as scheduled  0    25       

Reading List
Reading lists are managed at readinglists.liverpool.ac.uk. Click here to access the reading lists for this module.