Module Specification

The information contained in this module specification was correct at the time of publication but may be subject to change, either during the session because of unforeseen circumstances, or following review of the module at the end of the session. Queries about the module should be directed to the member of staff with responsibility for the module.
Title DIGITAL SYSTEM DESIGN
Code ELEC373
Coordinator Professor JS Smith
Electrical Engineering and Electronics
J.S.Smith@liverpool.ac.uk
Year CATS Level Semester CATS Value
Session 2021-22 Level 6 FHEQ Whole Session 15

Aims

To provide students with the ability to: Design and synthesise digital systems using Verilog and ASM. Understand the problems of meta-stability in digital systems. Design microprocessors using ASM techniques. Develop and test customised NIOS II systems using Altera's System on a Programmable Chip (SOPC) builder tool and Software Build Tools (SBT).


Pre-requisites before taking this module (other modules and/or general educational/academic requirements):

ELEC211 DIGITAL ELECTRONICS & MICROPROCESSOR SYSTEMS 

Co-requisite modules:

 

Learning Outcomes

(LO1) Ability to design digital systems using the ASM design method.

(LO2) Ability to implement digital systems using the Verilog Hardware Description Language.

(LO3) Understanding the internal operation of a MIPS processor.

(LO4) Ability to implement a SOPC system using Quartus Nios-II.

(S1) IT skills

(S2) Problem solving skills


Syllabus

 

Introducing Verilog for logic design and the required software and hardware tools for the assignments.
RTL Modelling - Explains Verilog's expressions, operators and continuous assignment for combinational and sequential circuits.
Behavioural Modelling - Explains the always and initial procedures, blocking and nonblocking procedural statements.
Algorithmic State Machine (ASM): Counters and Registers.
Sequential Circuits Examples
Metastability and Synchronisers.
ASMD charts and Multipliers
Tasks, Functions and Synthesis Tips.
Single-Cycle MIPS Processor Datapath and Control
Multicycle MIPS Processor Datapath and Control
Pipelined MIPS Processor
System on a Programmable Chip (SOPC) using Nios-II
Hardware testing and Design for Testability.


Teaching and Learning Strategies

Due to Covid-19, one or more of the following delivery methods will be implemented based on the current local conditions and the situation of registered students. It is anticipated that both a) & b) will be in operation for semester 1.
(a) Hybrid delivery, with social distancing on Campus
Teaching Method 1 - On-line asynchronous lectures
Description: Lectures to explain the material
Attendance Recorded: No
Notes: On average one per week

Teaching Method 2 - Synchronous face to face tutorials
Description: Tutorials on the Assignments and Problem Sheets
Attendance Recorded: Yes
Notes: On average one per fortnight

Teaching Method 3 - Campus based Laboratory Work Tutorials
Description: Laboratory Sessions to undertake tutorials and the Assignments
Attendance Recorded: Yes
Notes: 3 hours of supervised lab per week (10 weeks per semester)

(b) Fully online delivery an d assessment
Teaching Method 1 - On-line asynchronous lectures
Description: Lectures to explain the material
Attendance Recorded: No
Notes: On average one per week

Teaching Method 2 - On-line synchronous tutorials
Description: Tutorials on the Assignments and Problem Sheets
Attendance Recorded: Yes
Notes: On average one per fortnight

Teaching Method 3 - on-line Laboratory Work Tutorials
Description: Laboratory Sessions to undertake tutorials and the Assignments
Attendance Recorded: Yes
Notes: 3 hours of on-line supervised lab per week where students can contact demonstrators to provide support (10 weeks per semester)

(c) Standard on-campus delivery with minimal social distancing
Teaching Method 1 - Lecture
Description: Lectures to explain the material
Attendance Recorded: Yes
Notes: On average one per week

Teaching Method 2 - Tu torial
Description: Tutorials on the Assignments and Problem Sheets
Attendance Recorded: Yes
Notes: On average one per fortnight

Teaching Method 3 - Laboratory Work
Description: Laboratory Sessions to undertake tutorials and the Assignments
Attendance Recorded: Yes
Notes: 3 hours of supervised lab per week (10 weeks per semester)


Teaching Schedule

  Lectures Seminars Tutorials Lab Practicals Fieldwork Placement Other TOTAL
Study Hours 24

  4

60

    88
Timetable (if known)              
Private Study 62
TOTAL HOURS 150

Assessment

EXAM Duration Timing
(Semester)
% of
final
mark
Resit/resubmission
opportunity
Penalty for late
submission
Notes
Open Book Class Test 2 This is not an anonymous assessment. Assessment Schedule (When) :Week 12 - Semester 2  50 Minutes    10       
Open Book Class Test 1 There is a resit opportunity. This is not an anonymous assessment. Assessment Schedule (When) :Week 12 of semester 1  50 Minutes    10       
CONTINUOUS Duration Timing
(Semester)
% of
final
mark
Resit/resubmission
opportunity
Penalty for late
submission
Notes
MIPS Processor Design and Implementation There is a resit opportunity. Standard UoL penalty applies for late submission. This is not an anonymous assessment. Assessment Schedule (When) :Week 8   6 weeks    20       
NIOS II - Design example There is a resit opportunity. Standard UoL penalty applies for late submission. Assessment Schedule (When) :Week 12 Semester 2  4 Weeks    20       
Verilog design example Standard UoL penalty applies for late submission. This is not an anonymous assessment. Assessment Schedule (When) :Submit Week 12 Semester 1  6 weeks    25       
Basic Verilog design example There is a resit opportunity. Standard UoL penalty applies for late submission. This is not an anonymous assessment. Assessment Schedule (When) :Submit Week 7 Semes  5 weeks    15       

Reading List

Reading lists are managed at readinglists.liverpool.ac.uk. Click here to access the reading lists for this module.