Overview
Billions of microprocessors are sold annually, and modern society is critically dependent on them. This research project allows you to explore the frontiers of microprocessor dependability and enhance their reliability in a vast array of domains, ranging from everyday devices to highly specialised safety-critical systems. By collaborating with Arm, you will create innovative solutions on commercial-grade microprocessors and hardware platforms.
About this opportunity
Microprocessors underpin modern technology, from smartphones to autonomous vehicles and medical devices. In safety-critical domains alone, hundreds of millions are deployed in applications such as autonomous vehicles, medical devices, space exploration, defence, and avionics. Ensuring the functional safety and reliability of these systems is vital, as failures can have life-threatening consequences and cause significant financial and reputational losses for semiconductor companies. This PhD project addresses these challenges by advancing in-field testability, reliability, and fault-tolerant techniques for microprocessors, building on the group’s expertise in reliability, hardware-oriented security, testability and trust [1-5].
The project focuses on understanding and mitigating the dependability challenges of embedded microprocessors that underpin autonomous systems. As CMOS technology scales down and system complexity rises, new vulnerabilities emerge, making traditional reliability approaches insufficient. The candidate will develop fault models, fault-tolerant architectures, and test techniques capable of detecting, preventing, and managing hardware faults. Validation will include both software and hardware fault injection, analysis of soft error rates, and evaluation under varying process, voltage, and temperature conditions.
The project is structured to balance training, collaboration, and independent research. In the first phase, the candidate will focus on doctoral training, gaining expertise in quantitative dependability analysis, fault injection, and industrial evaluation techniques. This phase will include a placement at Arm (Cambridge, UK), which will offer hands-on experience with industrial tools, mentoring, and access to commercial IP, significantly enhancing the student’s employability. In subsequent years, the student will carry out independent research, thesis development, and refinement of fault-tolerant designs, ensuring the solutions are cost-effective and scalable. It is expected that the results will help microprocessor companies meet safety standards, such as ISO 26262, and offer critical design feedback to enhance the dependability of next-generation embedded processors. Regular meetings with academic supervisors and the industrial partner will facilitate knowledge exchange and support the translation of research outcomes into practical applications.
The project directly contributes to three National priority areas: Next Generation Computing (trustworthiness, reliability, energy efficiency), Semiconductor Technology (advancing embedded system design), and Future Communications (security, resilience, and trust). Beyond academic impact, it offers significant industrial relevance, with potential integration into next-generation microprocessor design workflows. The candidate will gain world-class training, enhanced employability, and the opportunity to contribute to long-term academic–industrial partnerships, positioning them at the forefront of research in dependable, safety-critical microprocessor systems.
Further reading
[1] A. Narang, B. Venu, S. Khursheed and P. Harrod, “An Exploration of Microprocessor Self-Test Optimisation Based On Safe Faults,” 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Athens, Greece, 2021, pp. 1-6. [Download link]
[2] A. L. H. Martínez, S. Khursheed, T. Alnuayri and D. Rossi, “Online Remaining Useful Lifetime Prediction Using Support Vector Regression,” in IEEE Transactions on Emerging Topics in Computing, vol. 10, no. 3, pp. 1546-1557, 1 July-Sept. 2022. [Download link]
[3] T. Alnuayri, S. Khursheed and D. Rossi, “On-Chip Age Estimation Using Machine Learning,” in IEEE Access, vol. 13, pp. 77334-77352, 2025. [Download link]
[4] G. Piliposyan and S. Khursheed, “PCB Hardware Trojan Run-Time Detection Through Machine Learning,” in IEEE Transactions on Computers, vol. 72, no. 7, pp. 1958-1970, July 2023. [Download link]
[5] V. Selis, and A. Marshall, “A Classification-Based Algorithm to Detect Forged Embedded Machines in IoT Environments”. IEEE Systems Journal, 13 (1). pp. 389-399, 2019. [Download link]